Through-silicon via (TSV)

 

 

Through-silicon via (TSV) has gained tremendous interest as a joining method for three-dimensional integrated circuit (3D IC) devices. Tungsten, polysilicon, and copper have been considered as filling metals for TSVs, and copper is most popular due to its low resistivity and the compatibility with copper interconnects.

 

Copper contamination raises many reliability issues in 3D iC, such as dielectric leakage and transistor degradation. Thermo-mechanical stress due to the coefficient of thermal expansion (CTE) mismatch between silicon wafer and copper TSVs causes several issues concerning yield loss, decreased reliability and degradation of device properties.

 

 

 

 

 

 

 

 

 

 

The research on the reliability of TSV in the above-mentioned studies are mainly focused on the issues caused by thermal processing.

 

We studied the failure of copper TSVs under BTS (biased thermal stress), by constructing a three-dimensional finite element model using the commercial package, ANSYS, based on the geometry of the copper TSV fabricated in this study.

 

1. J.-S. Hwang, S.-H. Seo, and W.-J. Lee, “Effect of Design Parameters on Thermomechanical Stress in Silicon of Through-Silicon Via,” J. Electron. Packag., vol. 138, no. 3, p. 031006, 2016.

2. S. Seo, J. Lee, J. Song, W. Lee, and A. M. Engineering, “굽힘응력을 받는 유연전자소자에서 중립축 위치의 제어 Control of Position of Neutral Line in Flexible Microelectronic System Under Bending Stress,” J. Microelectron. Packag. Soc., vol. 23, no. 2, pp. 1–6, 2016.

3. S. H. Seo, J. S. Hwang, J. M. Yang, W. J. Hwang, J. Y. Song, and W. J. Lee, “Failure mechanism of copper through-silicon vias under biased thermal stress,” Thin Solid Films, vol. 546, pp. 14–17, 2013.