Si-based dielectrics materials
Silicon oxide (SiO2) and silicon nitride (SiN) have been the most widely used dielectric materials in semiconductor manufacturing processing. Due to requirements such as excellent conformality or low processing temperature, the deposition method has been gradually converted from chemical vapor deposition (CVD) to atomic layer deposition (ALD).
SiO2
In the front-end process, SiO2 films are grown mainly by thermal oxidation or low-pressure chemical vapor deposition (LPCVD) at >700°C. However, poor step coverage and high process temperature of ultrathin LPCVD films became issues in the manufacturing of nanoscale devices with three-dimensional structures.
Low-temperature high-quality SiO2 thin films are desirable for applications to the gate spacers and self-aligned multiple patterning technology. High-temperature high-quality SiO2 thin films are requested for the ONO stacks in three-dimensional vertical NAND flash memory devices.
We have been studying the ALD of SiO2 using several types of precursors, including chlorides and non-chlorides.
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[SAM-24] H. Roh, H.-L. Kim, K. Khumaini, H. Son, D. Shin, W.-J. Lee, Effect of Deposition Temperature and Surface Reactions in Atomic Layer Deposition of Silicon Oxide Using Bis(diethylamino)silane and Ozone, Applied Surface Science 571 (2022) 151231. https://doi.org/10.1016/j.apsusc.2021.151231
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[Si2Cl6+Et3N]T.R. Mayangsari, J.M. Park, L.L. Yusup, J. Gu, J.H. Yoo, H. D. Kim, W.-J. Lee, Catalyzed Atomic Layer Deposition of Silicon Oxide at Ultralow Temperature Using Alkylamine, Langmuir. 34 (2018) 6660–6669. doi:10.1021/acs.langmuir.8b00147.
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[Si(NHEt)4]J.-K. Kim, K. Jin, J. Jung, S.-K. Rha, and W.-J. Lee, “Atomic Layer Deposition of SiO2 Thin Films Using Tetrakis(ethylamino)silane and Ozone,” J. Nanosci. Nanotechnol., vol. 12, no. 4, pp. 3589–3592, 2012.
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[Si2Cl6] S.-W. Lee, K. Park, B. Han, S.-H. Son, S.-K. Rha, C.-O. Park, and W.-J. Lee, “Atomic Layer Deposition of Silicon Oxide Thin Films by Alternating Exposures to Si2Cl6 and O3,” Electrochem. Solid-State Lett., vol. 11, p. G23, 2008.
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[SiH2Cl2] J.-H. Lee, U.-J. Kim, C.-H. Han, S.-K. Rha, W.-J. Lee, and C.-O. Park, “Investigation of Silicon Oxide Thin Films Prepared by Atomic Layer Deposition Using SiH2Cl2 and O3 as the precursors,” Jpn. J. Appl. Phys., vol. 43, no. 3, pp. L328–L330, 2004.
SiN
Silicon nitride film has been used as the gate spacers, etch stop layers, and the charge trap layer of three-dimensional vertical NAND flash memory devices. The conventional method to produce silicon nitride film was the LPCVD at >600°C in the front-end process (FEP) or plasma-enhanced CVD (PECVD) at <400°C in the back-end of line (BEOL) process. Poor step coverage and high process temperature of LPCVD SiN films became issues in the manufacturing of nanoscale devices. PECVD can lower the process temperature, but the film quality is very poor and the step coverage is much worse than LPCVD.
with three-dimensional structures.
Low-temperature high-quality plasma-enhanced ALD (PEALD) is desirable for SiN films in high-end logic devices. High-temperature high-quality thermal ALD is requested for the charge trap layer in three-dimensional vertical NAND flash memory devices.
We have been studying thermal ALD and PEALD of SiN using several types of precursors, including chlorides and non-chlorides.
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[PEALD; CSN-2] J.-M. Park, S.J. Jang, S.-I. Lee, W.-J. Lee, Novel Cyclosilazane-Type Silicon Precursor and Two-Step Plasma for Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride, ACS Appl. Mater. Interfaces. 10 (2018) 9155–9163. doi:10.1021/acsami.7b19741
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[PEALD; DTDN2-H2] J.-M. Park, S. J. Jang, L. L. Yusup, W.-J. Lee, and S.-I. Lee, “Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride Using a Novel Silylamine Precursor,” ACS Appl. Mater. Interfaces 8(32) (2016) 0865–20871. https://doi.org/10.1021/acsami.6b06175
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[Si3Cl8, Si2Cl6, SiH2Cl2, SiCl4] L.L. Yusup, J.-M. Park, T.R. Mayangsari, Y.-K. Kwon, W.-J. Lee, Surface reaction of silicon chlorides during atomic layer deposition of silicon nitride, Appl. Surf. Sci. 432 Part B (2018) 127-131. doi:10.1016/j.apsusc.2017.06.060.
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[Si2Cl6] L. L. Yusup, J.-M. Park, Y.-H. Noh, S.-J. Kim, W.-J. Lee, S. Park, and Y.-K. Kwon, “Reactivity of different surface sites with silicon chlorides during atomic layer deposition of silicon nitride,” RSC Adv. 6(72) (2016) 68515–68524.
- [Si2Cl6] K. Park, W. D. Yun, B. J. Choi, H. D. Kim, W. J. Lee, S. K. Rha, and C. O. Park, “Growth studies and characterization of silicon nitride thin films deposited by alternating exposures to Si2Cl6 and NH3,” Thin Solid Films, vol. 517, pp. 3975–3978, 2009.
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[SiH2Cl2] W. J. Lee, U. J. Kim, C. H. Han, M. H. Chun, S. K. Rha, and Y. S. Lee, “Characteristics of silicon nitride thin films prepared by using alternating exposures of SiH2Cl2 and NH3,” J. Korean Phys. Soc., vol. 47, no. November, pp. S598–S602, 2005.
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[SiCl4, SiH2Cl2] W. Lee, J. Lee, C. O. Park, and Y. Lee, “A Comparative Study on the Si Precursors for the Atomic Layer Deposition of Silicon Nitride Thin Films,” Korean J. Mater. Res., vol. 45, no. 5, pp. 1352–1355, 2004.
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[Co-reactants] T.R. Mayangsari, L.L. Yusup, R. Hidayat, T. Chowdhury, Y.-K. Kwon, W.-J. Lee, Reactivity of different nitriding agents with chlorine-terminated surface during atomic layer deposition of silicon nitride, Appl. Surf. Sci. 535 (2021) 147727. https://doi.org/10.1016/j.apsusc.2020.147727
3D Vertical NAND Application
Recently, three-dimensional stacked memory array devices were developed because they may provide a new low-cost scaling path to NAND flash. In three-dimensional flash memories, dielectric deposition with excellent step coverage and film quality is becoming critical. The aspect ratio of the vertical channel hole will be very high because the number of stacking layers is expected to be >200 [1]. Atomic layer deposition (ALD) is an ideal method to resolve these issues.
In our studies, we successfully deposited SiO2 and SiN by ALD technique using Si2Cl6 as the silicon precursor [2]. We also studies metal/oxide/nitride/oxide/Si (MONOS) charge trap memory devices. The memory characteristics of MONOS capacitor was examined with varying the thickness and deposition condition of each layer. The memory window, program and erase speed, retention, endurance were compared.
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S. Lee, "Technology scaling challenges and opportunities of memory devices," 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 1.1.1-1.1.8, doi: 10.1109/IEDM.2016.7838026.
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H.-G. Lee, "A study on the Charge Trap Memory Device Prepared by Atomic layer Deposition Method," MS Thesis, Sejong University (2013.2).